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cascadable if vgas with programmable rms detectors data sheet adl5336 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011C2012 analog devices, inc. all rights reserved. features pair of vgas with rms agc detectors vga and agc modes of operation continuous gain control range: 48 db noise figure (nf) = 6.8 db at maximum gain imd3 > 62 dbc for 1.0 v p-p composite output differential input and output multiplexed inputs for vga2 programmable detector agc setpoints programmable vga maximum gain power-down feature single 5 v supply operation applications point-to-multipoint radios instrumentation medical functional block diagram figure 1. general description the adl5336 consists of a pair of variable gain amplifiers (vgas) designed for cascaded if applications. the amplifiers have linear-in-db gain control and operate from low frequencies to 1 ghz. their excellent gain conformance over the control range and flatness over frequency are due to analog devices, inc., patented x-amp? architecture, an innovative technique for implementing high performance variable gain control. each vga has 24 db of gain control range. their maximum gain can be independently programmable over a 6 db range via the spi. the vgas can be cascaded to provide a total range of 48 db. when connected to a 50 source through a 1:4 balun, the gain is 6 db higher. the second vga has an spi programmable input switch that selects one of two external inputs. when driven from a 200 source or from a 50 source through a 1:4 balun, the noise figure (nf) for the composite amplifier is 6.8 db at maximum gain. the output of each vga can drive 100 loads to 5 v p-p maximum. each vga has an independent square law detector for autonomous, automatic gain control (agc) operation. each detector setpoint can be programmed independently through the spi from ?24 dbv to ?3 dbv in 3 db steps. when both vgas are arranged in agc mode and are programmed to the same setpoint, the composite nf increases to 9 db when backed off by 18 db from maximum gain. the adl5336 operates from a 5 v supply and consumes a typical supply current of 80 ma. when disabled, it consumes 4 ma. it is fabricated in an advanced silicon-germanium bicmos process and is available in a 32-lead exposed paddle lfcsp package. performance is specified over a ?40c to +85c temperature range. adl5336 09550-001 vcm1 vpos vpos com mode enbl inp1 inm1 vpos vpos com sdo data opp2 vcm2 com opm2 opp1 opm1 ip2 a im2 a com ip2b im2b gain1 dto1 gain2 dto2 comd vpsd le clk x 2 x 2 spi vga1 vga2
adl5336 data sheet rev. b | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision h istory ............................................................................... 2 specifications ..................................................................................... 3 timing diagrams .......................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function description s ............................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 17 circuit description ..................................................................... 17 gain control interface ............................................................... 18 input and output impedances .................................................. 18 agc operation ........................................................................... 18 register map a nd codes ................................................................ 19 applications information .............................................................. 20 basic connections ...................................................................... 20 supply decoupling ..................................................................... 20 input sign al path ........................................................................ 20 output signal path ..................................................................... 20 detector output and gain pin ................................................. 21 common - mode bypassing ....................................................... 21 serial port connections ............................................................. 21 mode and enable connections ................................................ 21 error vector magnitude (evm) ............................................... 21 effect of c agc on evm ............................................................... 22 agc in sensitivity to modulation type ................................... 22 effect of setpoint on evm ........................................................ 23 cascaded vga/agc performance .......................................... 23 evaluation board layout ............................................................... 25 bill of materials (bom) ............................................................. 28 evaluation board control software ......................................... 29 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 30 revision histo ry 2 /1 2 rev. a to rev. b changes to figure 70 ...................................................................... 25 changes to figure 71 and figure 72............................................. 26 changes to table 11 ........................................................................ 28 changes to figure 73 ...................................................................... 29 updated outline dimensions ....................................................... 30 6 /11 rev. 0 to rev. a changes to table 1 ............................................................................ 3 changes to typical performance charteristics section format .................................................................................. 8 changes to figure 7 and figure 10 ................................................. 8 changes to figure 1 1 to figure 16 .................................................. 9 changes to figure 17 to figure 22 ................................................ 10 changes to figure 23 and figure 26............................................. 11 inserted figure 53 and figure 56; renumbered s equentially .. 16 changes to figure 60 ...................................................................... 17 changes to figure 61 caption ....................................................... 18 changes to cascaded vga/agc performance section and figure 68 .......................................................................................... 24 changes to figure 72 ...................................................................... 26 2 /1 1 revision 0: initial version
data sheet adl5336 rev. b | page 3 of 32 specifications v s = 5 v, t a = 25 c, z s = 2 00 ?, z l vga 1 = 200 ?, z l vga 2 = 100 ?, rf input = ?20 dbm at 140 mhz , m ax imum gain setting for both vgas, unless otherwise noted. 1:4 balun voltage gain is not included. all dbm numbers are with respect to each vgas load impedance. table 1 . parameter test conditions /comments min typ max unit overall function frequency range 3 db bandwidth lf 1000 mhz maximum input inp1/inm1, i p2 a/i m2 a, ip2b/im2b differential 8 v p -p maximum output opp1/ o p m 1, opp2/ o p m 2 differential at p1db 5 v p -p ac input impedance vga1 differential across inp1, inm1 20 0 vga2 selected input differential across ip2 a, im2 a or ip2 b, im2 b 2 0 0 vga2 unselected input 10 k ac output impedance vga1 1 vga2 3 .5 gain control interface gain1/gain2, mode voltage gain range gain1/ gain2 from 0 v to 1 v vga1 gain code 00 ? 14. 6 +9. 7 db gain code 01 ? 12.2 +12 db gain code 10 ? 10 .3 + 13.8 db gain code 11 ? 8. 9 +15. 2 db vga2 gain code 00 ? 10.8 +1 3.4 db gain code 01 ? 8 . 2 + 15.9 db gain code 10 ? 6.6 + 17.7 db gain code 11 ? 4.7 + 19.5 db gain step response time 8.5 db gain step 5 ns gain slope vga1 mode = v s 35 mv/db vga2 35 mv/db gain error v gain x from 0.2 v to 0.8 v 0.2 db input impedance v gain x to com 4.6 m f = 140 mhz noise figure vga1, gain code 00, v gain = 1 v 7.4 db vga2, gain code 11, v gain = 1 v 7.1 db output ip3 vga1, gain code 00, v gain = 1 v 21 ( 28) dbv ( dbm ) output voltage level of 1.0 v p - p vga1, gain code 11, v gain = 1 v 18 ( 25) dbv ( dbm ) vga2, gain code 00, v gain = 1 v 26 ( 36) dbv ( dbm ) vga2, gain code 11, v gain = 1 v 24 ( 34) dbv ( dbm ) output p1db vga1, gain code 00, v gain = 1 v 3. 5 ( 10.5 ) dbv ( dbm ) vga1, gain code 11, v gain = 1 v 3.5 ( 10.5 ) dbv ( dbm ) vga2, gain code 00, v gain = 1 v 4 ( 14 ) dbv ( dbm ) vga2, gain code 11, v gain = 1 v 4 ( 14 ) dbv ( dbm )
adl5336 data sheet rev. b | page 4 of 32 parameter test conditions /comments min typ max unit f = 350 mhz noise figure vga1, gain code 00 , v gain = 1 v 8 db vga2, gain code 11, v gain = 1 v 7.7 db output ip3 vga1, gain code 00, v gain = 1 v 12 ( 19) dbv ( dbm ) output voltage level of 1.0 v p - p vga1, gain code 11, v gain = 1 v 10.5 ( 17.5 ) dbv ( dbm ) vga2, gain code 00, v gain = 1 v 18 ( 28) dbv ( dbm ) vga2, gain code 11, v gain = 1 v 16 ( 26) dbv ( dbm ) output p1db vga1, gain code 00, v gain = 1 v 0 ( 7 ) dbv ( dbm ) vga1, gain code 11, v gain = 1 v 0 ( 7 ) dbv ( dbm ) vga2, gain code 00, v gain = 1 v ? 1.5 ( + 8.5 ) dbv ( dbm ) vga2, gain code 11, v gain = 1 v ? 1.5 ( + 8.5 ) dbv ( dbm ) square law detectors dto1, dto2 output setpoint spi controlled, 3 db steps ? 24 ? 3 dbv output range 0.1 v s /2 v agc step response range 5 db input step, c agc = 0.1 f 1.5 m s digital logic le, clk, data, sdo input high voltage, v inh >2.2 v input low voltage, v inl <1.8 v input current, i inh /i inl <1 a input capacitance, c in 2 pf spi timing le, clk, data, sdo f clk 20 mhz t dh data hold time 5 ns t ds data setup time 5 ns t lh le hold time 5 ns t ls le setup time 5 ns t pw clk high pulse width 5 ns t d clk -to - sdo delay 5 ns power and enable vpos, vpsd, com, comd, enbl supply voltage range 4.5 5 5.5 v total supply current enbl = 5 v 80 ma disable current enbl = 0 v 4 ma disable threshold 2.3 v enable response time delay following low -to - high transition until device meets full specifications in vga mode 800 ns disable response time delay following high -to - low transition until device produces full attenuation in vga mode 20 ns
data sheet adl5336 rev. b | page 5 of 32 timing diagrams figure 2. write mode timing diagram figure 3. read mode timing diagram write bit lsb + 1 lsb t dh t ds t lh t ls t pw t clk notes 1. the first d at a bit determines whether the p art is writing t o or reading from the interna l 8-bit register. for a write oper a tion, the first bit should be a logic 1. the 8-bit word is then registered in t o the d at a pin on consecutive rising edges of the clock. clk le dat a lsb + 2 msb ? 1 msb lsb + 3 msb ? 3 msb ? 2 09550-002 09550-003 t lh t dh t ds t ls t pw t clk dc dc read bit dc dc dc dc dc lsb + 1 lsb clk le dat a sdo t d notes 1. the first data bit determines whether the part is writing to or reading from the internal 8-bit register. for a read operation, the first bit should be a logic 0. the 8-bit word is then updated at the sdo pin on consecutive falling edges of the clock. lsb + 2 lsb + 3 msb ? 3 msb ? 2 msb ? 1 msb dc dc
adl5336 data sheet rev. b | page 6 of 32 absolute maximum rat ings table 2 . parameter rating supply voltage s ( vp o s , vps d ) 5 .5 v le , clk , data , sdo vpos + 0. 5 v enbl, mode vpos + 0. 5 v i n p1, i n m1, ip2a, i m2 a, ip2b, im2b vpos + 0. 5 v o p p1, o p m1, o p p2, o p m2 vpos + 0. 5 v dto1, dto2, gain1, gain2 vpos /2 + 0. 5 v internal power dissipation 530 mw ja (with pad soldered to board) 37.4 c/w maximum junction temperature 150 c operating temperature range ? 40c to +85c storage temperature range ? 65c to +150c lead temperature (soldering , 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet adl5336 rev. b | page 7 of 32 pin configuration an d function descripti ons figure 4. pin configuration table 3 . pin function descriptions pin no. mnemonic description 1, 24 vcm1, vcm2 common - m ode voltages . de couple to common for ac - coupled operation. 2, 5, 14, 20, 23 vpos , vpsd analog and di gital positive supply voltage ( 4. 5 v to 5.5 v ) . 3 , 4 , 25, 26 , 2 8 , 2 9 inp1, inm1 , im2b, ip2b , im2a, ip2 a differential inputs . 200 input impedance; ac coupling recommended. 6, 13, 19, 2 7 , 32 com , comd analog and digital common . connect via lowest possible impedance to external circuit common. 7 mode gain mode control . pull high for vga mode, and p ull low for agc mode . 8 enbl chip enable . pull high to enable. 9 , 1 1 gain1, gain2 analog gain control ( 0 v to 1 v ) . 1 0 , 1 2 dto1, dto2 detector outputs ( 0.1 v to vp o s/2 r ange ). 15, 16, 17, 18 le, clk, data, sdo spi programming and data readout pins . cmos levels v low < 1.8 v, v high > 2 .2 v . 2 1 , 2 2 , 30, 31 op m2, opp2 , op m1, opp1 differential outputs . low output impedance; ac coupling recommended. ep exposed paddle . connect to low impedance ground pad. pin 1 indic a t or notes 1. exposed paddle. connect to low impedance ground pad. 1 vcm1 2 vpos 3 inp1 4 inm1 5 vpos 6 com 7 mode 8 enb l 24 vcm2 23 vpos 22 opp2 21 opm2 20 vpos 19 com 18 sdo 17 dat a 9 gain1 10 dt o1 1 1 gain2 12 dt o2 13 comd 14 vpsd 15 le 16 clk 32 com 31 opp1 30 opm1 29 ip2 a 28 im2 a 27 com 26 ip2b 25 im2b t op view (not to scale) adl5336 09550-004
adl5336 data sheet rev. b | page 8 of 32 typical performance characteristics v s = 5 v, t a = 25c, z s = 200 , z l vga1 = 200 , z l vga2 = 100 , rf input = ?20 dbm at 140 mhz, unless otherwise noted. gain code = 11, v gain = 1 v, setpoint code = 000, mode = 5 v (vga mode) for both amplifiers, unless otherwise noted. figure 5. gain vs . frequency over v gain at gain code 11 for vga1 figure 6. gain vs. freque ncy over gain code at v gain = 0.5 v for vga1 figure 7. gain vs. v gain over frequency at gain code 11 for vga1 figure 8. gain vs . frequency over v gain at gain code 11 for vga2 figure 9. gain vs. frequency over gain code at v gain = 0.5 v for vga2 figure 10. gain vs. v gain over frequency at gain code 11 for vga2 ?40 ?30 ?20 ?10 0 10 20 10m 100m 1g voltage gain (db) frequency (hz) 09550-005 0mv 200mv 400mv 600mv 800mv 1000mv gain1 ?25 ?20 ?15 ?10 ?5 0 5 100m 1g voltage gain (db) frequency (hz) gain code 00 gain code 01 gain code 10 gain code 11 09550-006 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?15 ?10 ?5 0 5 10 15 20 0 100 200 300 400 500 600 700 800 900 1000 error (db) v o l t age gain (db) gain1 (mv) 140mhz 350mhz 140mhz 350mhz 09550-007 ?50 ?40 ?30 ?20 ?10 0 10 20 30 10m 100m 1g voltage gain (db) frequency (hz) 0mv 200mv 400mv 600mv 800mv 1000mv gain2 09550-008 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 10m 100m 1g voltage gain (db) frequency (hz) gain code 00 gain code 01 gain code 10 gain code 11 09550-009 error (db) ?4 ?3 ?2 ?1 0 1 2 3 4 0 100 200 300 400 500 600 700 800 900 1000 voltage gain (db) gain1 (mv) ?5 0 5 10 15 20 25 140mhz 350mhz 140mhz 350mhz 09550-010
data sheet adl5336 rev. b | page 9 of 32 figure 11. gain conformance over temperature for vga1 figure 12. oip3 vs. v gain over gain code for vga1 figure 13. oip3 vs. supply voltage at v gain = 0.5 v for vga1 figure 14. gain conformance over temperature for vga2 figure 15. oip3 vs. v gain over gain code for vga2 figure 16. oip3 vs. supply voltage at v gain = 0.5 v for vga2 error (db) ?3 ?2 ?1 0 1 2 3 4 ?15 ?10 ?5 0 5 10 15 20 0 100 200 300 400 500 600 700 800 900 1000 vol t age gain (db) gain1 (mv) ?40c +25c +85c ?40c +25c +85c 09550-011 0 5 10 15 20 25 30 35 ?7 ?2 3 8 13 18 23 28 0 100 200 300 400 500 600 700 800 900 1000 oip3 (dbm re: 200 ? ) oip3 (dbv) gain1 (mv) gain code 11 gain code 00 09550-114 0 5 10 15 20 25 30 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 oip3 (dbm re: 200 ? ) vpos (v) 09550-015 ?7 ?2 3 8 13 18 23 oip3 (dbv) error (db) ?4 ?3 ?2 ?1 0 1 2 3 4 0 100 200 300 400 500 600 700 800 900 1000 voltage gain (db) gain1 (mv) ?10 ?5 0 5 10 15 20 25 ?40c +25c +85c ?40c +25c +85c 09550-014 0 5 10 15 20 25 30 35 40 0 100 200 300 400 500 600 700 800 900 1000 oip3 (dbm re: 100 ? ) gain2 (mv) 09550-017 gain code 11 gain code 00 ?10 ?5 0 5 10 15 20 30 25 oip3 (dbv) 0 5 10 15 20 25 30 35 40 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 oip3 (dbm re: 100 ? ) vpos (v) 09550-018 ?10 ?5 0 5 10 15 20 30 25 oip3 (dbv)
adl5336 data sheet rev. b | page 10 of 32 figure 17 . oip3 vs. frequency over temperature for vga1 figure 18 . op1db vs. v gain over gain code for vga1 figure 19 . op1db vs. frequency over temperature for vga1 figure 20 . oip3 vs. frequency over temperature for vga2 figure 21 . op1db vs. v gain over gain code for vga2 figure 22 . op1db vs. frequency over temperature for vga2 0 5 10 15 20 25 30 35 40 0 50 100 150 200 250 300 350 400 450 500 oip3 (dbm re: 200?) frequenc y (mhz) ?40c +25c +85c 09550-013 ?7 ?2 3 8 13 18 23 33 28 oip3 (dbv) 0 2 4 6 8 10 12 14 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 op1db (dbm re: 200?) gain1 (v) 09550-020 gain code 11 gain code 00 ?7 ?5 ?3 ?1 1 3 7 5 op1db (dbv) ?5 ?3 ?1 1 3 5 7 9 1 1 13 15 0 50 100 150 200 250 300 350 400 450 500 op1db (dbm re: 200? ) frequenc y (mhz) ?40c +25c +85c 09550-019 ?12 ?10 ?8 ?6 ?4 ?2 0 2 8 4 6 op1db (dbv) 0 5 10 15 20 25 30 35 40 45 50 0 50 100 150 200 250 300 350 400 450 500 oip3 (dbm re: 100?) frequenc y (mhz) ?40c +25c +85c 09550-016 ?10 ?5 0 5 10 15 20 30 35 40 25 oip3 (dbv) 0 2 4 6 8 1 0 1 2 1 4 1 6 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 . 0 op1db (dbm re: 100?) gain2 (v) 09550-022 gain code 1 1 gain code 00 ?10 ?8 ?6 ?4 ?2 0 2 4 6 op1db (dbv) 0 2 4 6 8 10 12 14 16 0 50 100 150 200 250 300 350 400 450 500 op1db (dbm re: 100?) frequenc y (mhz) ?40c +25c +85c 09550-021 ?10 ?8 ?6 ?4 ?2 0 2 4 6 op1db (dbv)
data sheet adl5336 rev. b | page 11 of 32 figure 23 . op1db vs. supply voltage for vga1 figure 24 . noise figure vs. v gain1 over supply and temperature for vg a1 figure 25 . noise figure vs. frequency over maximum gains for vga1 figure 26 . op1db vs. supply voltage for vga2 figure 27 . noise figure vs. v gain2 over supply and temperature for vga2 figure 28 . noise figure vs. frequency over maximum gains for vga2 0 2 4 6 8 10 12 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 op1db (dbm re: 200?) vpos (v) 09550-023 ?7 ?5 ?3 ?1 1 3 5 op1db (dbv) 0 5 10 15 20 25 30 35 40 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 noise figure (db) v gain1 (v) 4.5vdc/?40c 5.0vdc/?40c 5.5vdc/?40c 4.5vdc/+25c 5.0vdc/+25c 5.5vdc/+25c 4.5vdc/+85c 5.0vdc/+85c 5.5vdc/+85c 09550-030 09550-033 3 4 5 6 7 8 9 10 1 1 12 13 0 100 200 300 400 500 600 700 800 noise figure (db) frequenc y (mhz) gain code 00 gain code 01 gain code 10 gain code 11 0 2 4 6 8 10 12 14 16 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 op1db (dbm re: 100?) vpos (v) 09550-026 ?10 ?8 ?6 ?4 ?2 0 2 4 6 op1db (dbv) 0 5 10 15 20 25 30 35 40 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 noise figure (db) v gain2 (v) 4.5vdc/?40c 5.0vdc/?40c 5.5vdc/?40c 4.5vdc/+25c 5.0vdc/+25c 5.5vdc/+25c 4.5vdc/+85c 5.0vdc/+85c 5.5vdc/+85c 09550-031 09550-034 5 6 7 8 9 10 1 1 12 13 14 15 0 100 200 300 400 500 600 700 800 noise figure (db) frequenc y (mhz) gain code 00 gain code 01 gain code 10 gain code 11
adl5336 data sheet rev. b | page 12 of 32 figure 29 . imd3 vs. v gain over frequency and gain code, v out = 1 v p - p composite, 2 mhz spac ing for vga1 figure 30 . v gain step response (vga mode) over gain step, v in = 100 mv p - p for vga1 figure 31 . supply current (vga1 switch disabled) over temperature figure 32 . imd3 vs. v gain over frequency and gain code, v out = 1 v p - p composite, 2 mhz spacing for vga2 figure 33 . v gain step response (vga mode) over gain step, v in = 100 mv p - p for vga2 figure 34 . su pply current (vga2 switch enabled) over temperature 0 10 20 30 40 50 60 70 80 0 100 200 300 400 500 600 700 800 900 1000 imd3 (dbc) gain1 (mv) gain code 11, 140mhz gain code 00, 140mhz gain code 00, 350mhz gain code 11, 350mhz 09550-029 09550-036 gain1 rf output time (100ns/div) rf output (20mv/div) gain1 (100mv/div) 0 10 20 30 40 50 60 70 80 90 ?40 ?20 0 20 40 60 80 supp l y current (ma) temper a ture (c) 09550-131 0 10 20 30 40 50 60 70 0 100 200 300 400 500 600 700 800 900 1000 imd3 (dbc) gain2 (mv) gain code 00, 140mhz gain code 11, 140mhz gain code 00, 350mhz gain code 11, 350mhz 09550-132 09550-039 gain2 rf output time (100ns/div) rf output (20mv/div) gain2 (100mv/div) gain2 rf output 0 5 10 15 20 25 30 35 40 45 50 ?40 ?20 0 20 40 60 80 supp l y current (ma) temper a ture (c) 09550-134
data sheet adl5336 rev. b | page 13 of 32 figure 35 . input resistance and capacitance vs. frequency for vga1 figure 36 . s11 (re: 200 ?) magnitude and phase vs. v gain for vga1 figure 37 . s11 (re: 50 ?) vs. frequency over v gain for vga1 figure 38 . input resistance and capacitance vs. frequency for vga2 figure 39 . s11 (re: 200 ?) magnitude and pha se vs. v gain for vga2 figure 40 . s11 (re: 50 ?) vs. frequency over v gain for vga2 0 0.5 1.0 1.5 2.0 2.5 0 50 100 150 200 250 10m 100m p aralle l input ca p aci t ance (pf) p aralle l input resis t ance ( ?) frequenc y (hz) gain code 00 gain code 11 gain code 00 gain code 11 09550-041 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 100 200 300 400 500 600 700 800 900 1000 s1 1 phase (degrees) s1 1 magnitude (db) gain1 (mv) 09550-042 09550-043 10mhz 500mhz 3ghz gain code 00 gain code 1 1 0 0.5 1.0 1.5 2.0 2.5 0 50 100 150 200 250 10m 100m p aralle l input ca p aci t ance (pf) p aralle l input resis t ance ( ?) frequenc y (hz) gain code 00 gain code 11 gain code 00 gain code 11 09550-044 ?120 ?1 15 ?1 10 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 0 200 400 600 800 1000 s1 1 phase (degrees) s1 1 magnitude (db) gain2 (mv) 09550-045 09550-046 10mhz 500mhz 3ghz gain code 00 gain code 1 1
adl5336 data sheet rev. b | page 14 of 32 figure 41 . s22 (re: 50 ?) vs. v gain over gain code for vga1 figure 42 . s22 (re: 200 ?) magnitude and phase vs. v gain for vga1 figure 43 . series output resistance and inductance vs. frequency over v gain for vga1 figure 44 . s22 (re: 50 ?) vs. v gain over gain code for vga2 figu re 45 . s22 (re: 100 ?) magnitude and phase vs. v gain for vga2 figure 46 . series output resistance and inductance vs. frequency over v gain for vga2 09550-047 10mhz 500mhz 3ghz gain code 00 gain code 1 1 100 1 10 120 130 140 150 160 170 180 190 200 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 0 100 200 300 400 500 600 700 800 900 1000 s22 phase (degrees) s22 magnitude (db) gain1 (mv) 09550-048 ?1 1 0 2 3 4 5 0 1 2 3 4 5 6 7 8 9 10 10m 100m series output induc t ance (nh) series output resis t ance ( ?) frequenc y (hz) gain code 00 gain code 11 gain code 00 gain code 11 09550-049 09550-050 10mhz 500mhz 3ghz gain code 00 gain code 1 1 80 90 100 1 10 120 130 140 150 160 170 180 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 0 200 400 600 800 1000 s22 phase (degrees) s22 magnitude (db) gain2 ( mv) 09550-051 1 0 ?1 2 3 4 5 6 7 8 0 5 10 15 20 25 30 35 40 10m 100m series output induc t ance (nh) series output resis t ance ( ?) frequenc y (hz) gain code 00 gain code 11 gain code 00 gain code 11 09550-052
data sheet adl5336 rev. b | page 15 of 32 figure 47. rssi step response (agc mode) for vga1 figure 48. v out vs. input power (p in ) over frequency (agc mode) for vga1 figure 49. v out vs. input power (p in ) over setpoint (agc mode) for vga1 figure 50. rssi step response (agc mode) for vga2 figure 51. v out vs. input power (p in ) over frequency (agc mode) for vga2 figure 52. v out vs. input power (p in ) over setpoint (agc mode) for vga2 time (1ms/div) rf input (500mv/div) rf output (500mv/div) deto1 (100mv/div) 09550-053 rf input rf output deto1 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 v out (v rms) p in (dbm) 140 mhz 350 mhz 09550-148 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 v out (v rms) p in (dbm) setpoint 000 setpoint 010 setpoint 100 setpoint 110 setpoint 001 setpoint 011 setpoint 101 setpoint 111 09550-149 time (1ms/div) rf input (200mv/div) rf output (200mv/div) deto2 (200mv/div) 0 9550-056 rf input rf output deto2 0 0.05 0.10 0.15 0.20 0.25 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 v out (v rms) p in (dbm) 140mhz 350mhz 09550-151 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 v out (v rms) p in (dbm) 09550-152 setpoint 000 setpoint 010 setpoint 100 setpoint 110 setpoint 001 setpoint 011 setpoint 101 setpoint 111
adl5336 data sheet rev. b | page 16 of 32 figure 53 . v out vs. input p ower (p in ) over temperature for vga1 figure 54 . amplifier isolation vs. frequency; vga1 differential input (in1) to vga2 differential output (out2); vga2 differential input a (in2(a)) to vga1 differential output (out1) figure 55 . cmrr vs. frequency for vga1 figure 56 . v out vs. input p ower (p in ) over temperature for vga2 figure 57 . vga2 input switch isolation vs. frequency; vga2 disabled differential input (in2(a), in2(b)) to vga2 differential output (out2) figure 58 . cmrr vs. frequency for vga2 0 0.05 0.10 0.15 0.20 0.25 0.30 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 v out (v rms) p in (dbm) ?40c +25c +85c 09550-157 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100 volt age gain isol a tion (db) frequenc y (mhz) in2(a) to out1 in1 to out2 09550-059 0 10 20 30 40 50 60 70 80 10m 100m 1g cmrr (db) frequenc y (hz) 09550-154 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 v out (v rms) p in (dbm) 09550-158 ?40c +25c +85c ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 volt age gain isol a tion (db) frequenc y (mhz) in2(a) to out2 in2(b) to out2 09550-062 0 10 20 30 40 50 60 10m 100m 1g cmrr (db) frequenc y (hz) 09550-156
data sheet adl5336 rev. b | page 17 of 32 theory of operation circuit description the adl5336 contains two differential vgas, each with a programmable, internally connected, square law detector. vga2 includes an input select switch that allows the user to choose between two sets of differential inputs. the signal path of each vga, shown in figure 59 and figure 60, consists of a variable input attenuator followed by a programmable gain amplifier (pga). the input attenuator is built from an 18-section resistor ladder, providing 1.34 db of attenuation at each successive tap point. the resistor ladder acts as a linear input attenuator, in addition to providing an accurate 200 input impedance. the variable transconductance (g m ) stages are used to select the attenuated signal from the appropriate tap point along the ladder and feed this signal to the fixed gain amplifier. to realize a continuous gain control function from discrete tap points, the gain interpolator creates a weighted sum of signals appearing on adjacent tap points by carefully controlling the variable g m stages. the weighted sum of the different tap points is fed into the programmable gain stage. the programmable gain stage achieves its different gain settings by changing the feedback network of the amplifier. the input attenuator and g m stages provide analog gain control of 24 db, whereas the programmable gain amplifier sets the maximum gain of each vga. table 4. vga gain range maximum gain word vga1 vga2 vga1 range (db) vga2 range (db) 0 0 ?14.5 to +9.5 ?10 to +14 0 1 ?12 to +12.0 ?7.1 to +16.9 1 0 ?10 to +14.0 ?5 to +19 1 1 ?8.4 to +15.6 ?3.1 to +20.9 figure 59. vga1 functional block diagram figure 60. vga2 functional block diagram attenuator ladder 200 ? 0db ?1.4db ?2.8db ?23.8db opp1 inp1 gain1 mode gain interpolator pga inm1 ?22.4db g m stages opm1 pga linear voltage gain: g = 3, 4, 5, 6 09550-065 pga linear voltage gain: g = 5, 7, 9, 11 ip2a im2a ip2b im2b attenuator ladder 200 ? 0db ?1.4db ?2.8db ?23.8db opp2 gain2 mode gain interpolator pga ?22.4db g m stages opm2 09550-066
adl5336 data sheet rev. b | page 18 of 32 gain control interface the adl5336 has a linear-in-db gain control interface that can operate in either a gain-up mode or gain-down mode. in the gain-up mode, with the mode pin pulled high, the gain increases with increasing gain voltages. in the gain-down mode, with the mode pin pulled low, the gain decreases with increasing gain voltages. in both modes of operation, the gain control slope is maintained at +37.5 db/v or ?38 db/v (depending on mode selection) over temperature, supply, and process as v gain varies from 100 mv to 900 mv. to form an agc loop with the on-board detector around the vga, the mode pin has to be pulled low. each vga has 24 db of gain range that can be shifted as the maximum gain is programmed. the gain functions for mode pulled high and low are given respectively by gain high (db) = 37.5 v gain ? 14 gain low (db) = ?38 v gain + 24.8 where v gain is expressed in volts. figure 61. gain and conformance error vs. v gain1 /v gain2 for gain code 11, and mode = 0 v and mode = 5 v for both vgas input and output impedances the adl5336 offers differential broadband, 200 input impedance. the output of each vga is a low impedance buffer with negative feedback within the programmable gain amplifier. the negative feedback reduces the output impedance at low frequencies, but the output impedance increases with increasing frequency above 300 mhz. agc operation the internally connected square law detectors are connected to the outputs of the vgas through a programmable attenuator. the detector compares the output of the attenuator to an internal reference of 63 mv rms. the agc loop is closed by connecting the dto1/dto2 pins to the gain1/gain2 pins, and having the mode pin pulled low, configuring the vgas for a negative gain slope. if the attenuator is programmed to pass the full vga output, the agc forces the output of the vga to 63 mv rms, as long as the gain required is within the gain range of the vga. if the attenuator is programmed to attenuate the vga output by 21 db (setpoint word 111) and the agc loop is closed, the agc function forces the vga output to 707 mv rms. if the gain required to achieve the programmed target output level is out of the vga range, the gainx pin rails to either vpos/2 or gnd. if the amplifier is operated in vga mode or the detector is not otherwise being used, the setpoint should be programmed to maximum attenuation so that the vga output does not overdrive the input to the detector, adversely affecting both the detector and vga output. figure 62. rms detection diagram (sho ws the signal path from vga1/vga2 output to squarer cell) ?4 ?3 ?2 ?1 0 1 2 3 4 ?15 ?10 ?5 0 5 10 15 20 25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 conformance error (db) gain (db) v gain1 /v gain2 (v) vga1 gain vga1 gain vga2 gain vga2 gain vga1 error vga1 error vga2 error vga2 error 0 9550-067 x 2 dto1/ dto2 gain1/ gain2 ref 63mv rms +? spi setpoint control c agc x 2 09550-073
data sheet adl5336 rev. b | page 19 of 32 register map and cod es table 5 . register map msb lsb b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 vga2 maximum gain vga1 maximum gain vga2 switch vga2 setpoint vga1 setpoint table 6 . rms output setpoint map setpoint word rms output (mv rms/dbv) 0 0 0 +62.5/?24 0 0 1 +88/?21 0 1 0 +125/?18 0 1 1 +176/?15 1 0 0 +250/?12 1 0 1 +353/?9 1 1 0 +500/?6 1 1 1 +707/?3 table 7 . vga2 input switch logic vga2 switch selected input 0 ip2a, im2a 1 ip2b, im2b table 8 . maximum gain map maximum gain word vga1 maximum gain (db) vga2 maximum gain (db) 0 0 9.5 14 0 1 12.0 16.9 1 0 14.0 19 1 1 15.6 20.9
adl5336 data sheet rev. b | page 20 of 32 applications informa tion basic connections the basic connections for a typical adl5336 application are show n in figure 63. s upply d ecoupling a nominal supply voltage of 5.0 v should be applied to the supply pins. the supply voltage should be between the limits of 4.5 v and 5.5 v. all of the supply pins must be decoupled to ground with at least one low inductance, surface - mount ceramic capacitor of 0.1 f. place t hese decoupling capacitors as close as possible to the adl5336 device. the adl53 36 has an analog supply and a digital supply. take c are to separate the two supplies with a large surface - mount inductor of 33 h , and each supply must then be decoupled separately to their respective grounds through a 10 f capacitor. the adl5336 also has two separate grounds: an analog ground and a digital ground. again, a large surface - mount inductor of 33 h should be used to separate the grounds. i nput s ignal p ath the adl5336 has three input signal paths, two of which inputs go to vga2 via an internal switch , and the other input go es to vga1. each of the three pairs of input pins (inp1/inm1, ip2a/im2 a, and ip2b/im2 b ) has a differential input impedance of 200 ? . to obtain maximum power transfer, the driving source impedance also needs to be 200 ? . on the e valuation board, this is achieved via a 4:1 impedance ratio balun. the evaluation board schematic is shown in figure 70 . for more information on the input signal paths , refer to the input signal path section. the input common - mode voltage sits at roughly vpos/2 for both vgas, except on vga2; the nonselected input of vga2 has an input common - mode voltage that sits at roughly ground. output signal path there are two output signal paths on the adl5336 ; one signal path per vga. the output of vga1 can be ac - coupled into either of the inputs of vga2 , which cascades the two vgas, or ac - coupled into a 200 ? termination impedance. vga1 is designed to drive a 200 ? differential load, whe reas vga2 is designed to drive a 100 ? differential load. on the e valuation board, a 100 ? differential impedance is presented to the output of vga2. this is achieve via a 1:1 balun and a resistive matching network. for more information on th e evaluation board, see t he evaluation board schematic in figure 70. the output common - mode voltage on both vgas sits at roughly vpos/2. figure 63 . basic connections schematic im2 a im2b com ip2b ip2 a opm1 com opp1 vpos dat a vcm2 sdo com opm2 opp2 vpos gain2 dt o1 clk le dt o2 gain1 comd vpsd enb l inm1 vpos vpos adl5336 mode inp1 com vcm1 +5v +5v input 1 spi contro l vpos vpos +5v +5v output 1 input 3 output 2 input 2 output 1 balun input 3 balun output 2 balun input 1 balun input 2 balun 09550-075
data sheet adl5336 rev. b | page 21 of 32 detector output and gain pin the adl5336 has a pair of detector squaring cells. e ach squaring cell has a vga output applied to its input. this is shown figure 1 and figure 62. these on - board detector squaring cells are used to achieve an agc function with the vg as. each of the squared outpu t signals is compared to a reference signal and the difference is then output in a current - mode signal. the dto1 pin is the detector squaring cell output that ta ps off of the output vga1 , and the d to2 pin is the detector squaring cell output that taps off of the output of vga2. by shorting the d to1 and gain1 pins together and putting a capacitor to ground on the d to1/ gain1 node, the agc function can be achieve d using vga1. the same connections can be done to d to2 and gain2 to achieve the agc function u sing vga2. t he mode pin must be pulled low for the agc function. for more information on the detector squaring cells and the agc function, refer to the agc operation section. for information concerning the capacitor value used , refer to the theory of operation section . common - mode bypassing decouple the two common - mode pins, vcm1 (pin 1) and vcm2 (pin 24), of the adl5336 using low inductance, surface - m ount ceramic capacitors. the evaluation board has 0 .1 f capacitor values for each of the common - mode pins (see figure 70) . serial port connections the spi port of the adl5336 write s data into the device and read s data out of it . the spi port controls max imum vga ga in levels, output setpoint levels, and vga2 input selection. i t is recommended to put low - pass rc filtering on the spi lines to filter out any high frequency glitches if reading and writing to the spi port becomes problematic . capacitors c26 through c29 , shown in figure 70, can be populated, along with replacing the standard 0 ? jumper resistors (r9 to r12) to make an appropriate low - pass rc filter net work on each spi line. mode and enable connections the adl5336 can have both a positive and negative gain slope. this function is controlled by the mode pin. when the mode is pulled high , it p ut s each vga into traditional vga mode, where the gain slope is positive. when the mode pin is pulled to ground , both vgas have a negative gain slope , which is needed to obtain an agc function with either vga. the mode threshold voltage levels are: v mode > 3 v for the positive gain slope and v mode < 2 v for the negative gain slope. pulling the enbl pin high enables the part and allows for normal operation. if the enbl pin is pulled low, then the adl5336 power s down and only draw s approximately 4 ma of supply current. error vector magnitu de ( evm ) evm is a measure used to quantify the performance of a digital radio transmitter or receiver by measuring the fidelity of the digital signal transmitted or received. various imperfections in the link, such as magnitude and phase imbalance, noise, and distortion, cause the constellation points to deviate from their ideal locations. in general, as signal power increases, the distortion components increase. a typical receiver ex hibits the three following distinct evm limitations vs. the received input signal power: ? at large enough signal levels, where the distortion components due to the harmonic nonlinearities in the device are falling in - band, evm degrades as signal levels incr ease. ? at medium signal levels, where the signal chain behaves in a linear manner and the signal is well above any notable noise contributions, evm has a tendency to reach an optimal level determined dominantly by either the quadrature accuracy and i/q gai n match of the signal chain or the precision of the test equipment. ? as signal levels decrease, such that noise is a major contributor, evm performance vs. the signal level exhibits a decibel - for - decibel degradation with decreasing signal level. at these lo wer signal levels, where noise is the dominant limitation, decibel evm is directly proportional to the snr .
adl5336 data sheet rev. b | page 22 of 32 effect of c agc on evm the choice of c agc is a compromise of averaging time constant, response time, and carrier leakage. if c agc is selected to be too small to speed up the response time, the agc loop could start tracking and leveling any amplitude envelope and corrupt the constellation. the agc loop bandwidth (bw) is given by the equation bw loop = 1/(2 r agc c agc ) where r agc i s the on - chip equivalent resistance of the loop. by increasing c agc (which decreases the loop bw) , evm can be improved becau se the signal is outside of the agc loop bw , and therefore, the agc no longer level s the amplitude envelope of the signal. figure 64 illustrates this behavior with three different agc capacit or values while the adl5336 vgas are cascaded. there is a drastic degradation of evm wh en the smaller capacitor values are used. this example uses a 16 qam modulated signal at 4.5 msym/sec using a pulse shaping filter and an alpha of 0.35. the frequency used was 140 mhz and output setpoints for both vgas were 250 mv rms. both vgas were set t o max imum gain codes of 11. figure 64 . evm vs. rf input power over several c agc values agc insensitivity to modulation type given that c agc is chosen correctly for the symbol rate of the modulated signal and carrier frequency , evm should not degrade much with different modulation types. the four different modulation types, and how evm changes with each, are shown in figure 65 . there is a n approximately 4 db spread across the curves. all modulated signals were set t o 4.5 msym/sec using a pulse shaping filter and an alpha of 0.35. the frequency used was 140 mhz. c ag c = 0.1 f and output setpoints for both vgas were 250 mv rms. both vgas were set to max imum gain codes of 11. figure 65 . evm vs. rf input power over several modulation t ypes ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 15 25 evm (db) rf input power (dbm) c agc = 0.1 f c agc = 1000pf c agc = 100pf 09550-072 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 15 25 evm (db) rf input power (dbm) 16qam 256qam qpsk 8psk 09550-070
data sheet adl5336 rev. b | page 23 of 32 effect of setpoint on evm while in agc mode, the evm can degrade depending on the output setpoint each vga is set to. there is a strong relationship between the output setpoint of vga2 and evm performance while the output setpoint of vga1 is held constant. conversely, the evm does not change much while the output setpoint of the vga2 is held constant and the output setpoint of vga1 is changed. this behavior can be seen in figure 66 where several different setpoints of both vgas were tested. this example uses a 16 qam modulated signal at 4.5 msym/sec using a pulse shaping filter and an alpha of 0.35.the frequency used was 140 mhz and c agc = 0.1 f. both vgas were set to maximum gain codes of 11. figure 66. evm vs. rf input power over several setpoints figure 67. evm vs. rf input power while vga1 setpoint held constant to 250 mv rms and vga2 setpoint swept; vga1/vga2 gain code = 11 cascaded vga/agc performance the adl5336 is designed for easy ca scading of the two vgas. cascading vgas decreases the overall noise figure by keeping as much gain as possible before the final gain stage/noise source. a single x-amp has constant output referred noise. for an 8 db nf amplifier, with 36 db maximum gain, in a 200 matched system, output referred noise v n, rto = 144 nv/hz. rto, the noise contribution from the source, is the constant source noise multiplied by the gain (as the gain is reduced, the noise contribution from the source decreases). measuring noise figure as 20 log10 (total noise/noise from source), the db-for-db degradation in nf typical of this architecture can be seen. when the gain is partitioned into two vgas, consider 18 db each. if each has an 8 db nf, then each has an rto noise of 18 nv/hz, including the source noise, and 16.5 nv/hz, excluding the source noise. at maximum gain, the total rto noise is 145 nv/hz. as overall gain is decreased, the gain of vga2 is decreased first. when the gain of vga2 is decreased by 6 db, the noise contributions from the source and vga1 both decrease by 6 db for an overall rto noise of the system that falls to 74 nv/hz. when vga1 and vga2 are cascaded and operating in agc mode, setpoint programming affects dynamic range. the noise measured at the output of vga1 is relatively constant across gain, which is a feature common to x-amp vgas. however, measured at the output of vga2, the noise contribution from vga2 is constant, but the noise contribution from vga1 depends on the gain of vga2. for a given overall gain (vga1 and vga2), the gain partitioning between vga1 and vga2 controls total rto noise and distortion. to illustrate, consider the case where both vgas are programmed to a maximum gain of 14 db and the setpoint of vga2 is 101, or 353 mv rms. gain and signal levels can also be looked at when the setpoint of vga1 is programmed to 011, 101, and 111, 176 mv rms, 353 mv rms, and 707 mv rms (see table 9). table 9. total cascaded output noise v i (mv rms) a v1 (db) v o1 (mv rms) a v2 (db) v o (mv rms) n 1 n 2 n total 176 0 176 +6 353 20 10 22.4 176 6 353 0 353 10 10 14.1 176 12 707 ?6 353 5 10 11.2 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 15 25 evm (db) rf input power (dbm) vga1 88mv rms, vga2 250mv rms vga1 250mv rms, vga2 250mv rms vga1 707mv rms, vga2 250mv rms vga1 250mv rms, vga2 88mv rms vga1 250mv rms, vga2 500mv rms vga1 250mv rms, vga2 125mv rms vga1 250mv rms, vga2 176mv rms 09550-071 0 0.5 1.0 1.5 2.0 2.5 v gain1 /v gain2 (v) evm (db) ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?65 ?55 ?45 ?35 ?25 ?15 ?5 5 15 25 rf input power (dbm) vga2 88mv rms vga2 125mv rms vga2 176 mv rms vga2 250mv rms vga2 500mv rms vgain2 250/88 vgain2 250/125 vgain2 250/176 vgain2 250/250 vgain2 250/500 09550-165 v gain1
adl5336 data sheet rev. b | page 24 of 32 as the setpoint of vga1 increases, the total output noise decreases. linearity limits how high the setpoint of vga1 for a given system can be programmed. for two equal sinusoidal tones, 353 mv rms corresponds to 1.4 v p - p, whe reas 707 mv rms corresponds to 2.8 v p - p. for a 1.4 v p - p composite output, imd3 is approximately ?65 dbc; however, for a 2.8 v p - p composite output , imd3 is theoretically 12 db worse at ?53 dbc. for each vga, total rto noise increases at higher maximum - gain settings; therefore, the overall combination of maximum gain should be minimized while still satisfying all system require ments with adequate margin. in linear terms, the noise figure of the cascaded amplifiers can be given by nf cas = nf vga1 + ( nf vga2 ? 1)/ g vga1 because bo th vgas are x - amps, the noise figure of each vga degrades db - for - db as the gain of each vga decreases. this is due to the attenuation ladder on the input that attenuates the signal before the signal is gained up. if only the gain of the second vga is chang ing, the cascaded noise figure does not change appreciably because the noise figure of the second vga is being divided by the constant gain of the first vga. when the gain of vga2 drops to the minimum and the input signal level is still decreasing , vga1 ta kes over and i ts gain starts to change. the cascaded noise figure increases db - for - db while the gain of vga1 decreases. while cascading the vgas, keeping intermodulation distortion components low is at direct odds with keeping noise figure and output noise density low. it can be shown that the third - order intercept of a cascaded system in linear terms is p3 = 1/(1/( g vga2 p 3_vga1 ) + 1/ p 3_vga2 ) where p 3_vga1 and p 3_vga2 are the third - order intercept points of each vga in w atts. thus, when the overall ip3 is the largest (distortion is the smallest), the gain of vga2 is at its maximum. vice - versa, when the gain of vga2 is at its minimum, the overall ip3 is the smallest, and distortion is at its maximum. table 10 provides conditions for optimization for the output noise density, noise figure, and distortion parameters. table 10 . optimized conditions vga1 gain vga2 gain output noise minimum minimum noise figure maximum maximum 1 imd/ip3 maximum 2 maximum 1 having the gain of vga2 at maximum does not change the overall noise figure much due to the noise figure contribution of vga2 being divided by the gain of vga1. 2 imd levels do not change much over the x - amp gain range, but best imd levels are achieved at high gains. when starting from a very small input power, such that neither vga h as reached their respective set points , and the analog gain of both vgas is forced to its maximum, the casc aded oip3 is at its maximum , while the cascaded noise figure is at its minimum . as the input power is increase d , each vga keep s its gain at maximum until its respective setpoint is reached , a t which point the gain of the vga (whose setpoint has been reached) decrease s to accom o date the increa ced input power and thus chang es the cascaded oip3 and noise figure. figure 68 shows how the oip3 changes while input power is varied in agc mode , which consequently changes the analog gains of the vgas. the setpoint of vga2 is fixed to 100 (or 250 mv rms ) , and the setpoint of vga1 is changed from 001 (88 mv rms) t o 100 (250 mv rms) , and finally , to 111 (707 mv rms). figure 68 . o ip3 vs. overall voltage gain over several s etpoints ; vga1 gain code = 11 and vga2 gain code = 00 figure 69 . n oise f igure vs. overall voltage gain over several setpoints; vga1 gain code = 11 and vga2 gain code = 00 figure 69 shows how the nf changes while the input power is varied in agc , which again, consequently changes the analog gains of the vgas . the setpoint of vga2 is still fixed to 100 (250 mv rms) , and t he changes made to the setpoint of vga1 is the same as before. 10 15 20 25 30 35 0 5 10 15 20 25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 oip3 (dbv) overal l vo lt age gain (db) low tone, setpoint = 001 high tone, setpoint = 001 low tone, setpoint = 100 high tone, setpoint = 100 low tone, setpoint = 111 high tone, setpoint = 111 09550-076 oip3 (dbm re: 100?) 0 10 20 30 40 50 60 ?20 ?10 0 10 20 30 noise figure (db) overal l vo lt age gain (db) setpoint = 001 setpoint = 100 setpoint = 111 09550-077
data sheet adl5336 rev. b | page 25 of 32 evaluation board lay out an evaluation board is available for testing the adl5336 . the evaluation board schematic is shown in figure 70. table 11 provides the component values and suggestions for modifying the component values for the various modes of operation. figure 70 . evaluation board schematic 09550-081 32 31 30 29 28 27 26 25 9 10 1 1 12 13 14 15 16 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 im2a im2b com ip2b ip2a opm1 com opp1 vpos data vcm2 sdo com opm2 opp2 vpos gain2 dto1 clk le dto2 gain1 comd vpsd enbl inm1 vpos vpos mode inp1 com vcm1 adl5336 0.1f c6 c22 open c26 0? r12 dig_vpos vpos c2 10f 0.1f c7 vcm1 0.1f c5 vpos vpos 0.1f p5 gain1 r1 c12 0.1f 0? r2 c13 0.1f 0? p4 gain2 c16 0.1f open c27 0? r9 open c28 0? r 1 1 open c29 0? r10 c18 vpos 0.1f c25 0.1f c17 0.1f vcm2 c9 0.1f c8 0.1f output1 open r14 open r15 6 4 3 1 2 t2 0.1f c21 c4 0.1f 6 1 t1 2 4 3 0.1f c3 6 4 3 1 2 t4 0.1f c24 c15 0.1f c14 0.1f input3 open r4 open r3 c 1 1 0.1f c23 0.1f 2 1 0.1f c10 3 6 4 input2 t5 20 0.1f 0.1f c19 37.4? r6 37.4? r5 output2 r8 24.9? r7 24.9? 5 1 4 3 t3 vpos p2 vpos p3 c1 10f l2 33h l1 33h vposd vpos com comd input1 sdo d at a clk le open r13 legend net name t est point sm a input/output digital ground analog ground jumper ? ? ? ? ? ?
adl5336 data sheet rev. b | page 26 of 32 figure 71 . evaluation board schematic usb 56 55 54 53 52 51 50 49 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 35 36 37 38 39 40 41 42 pd7_fd15 pd4_fd12 pd6_fd14 pd5_fd13 gnd clkout gnd vcc pa5_fifoard1 pa2_sloe reset_n pa3_wu2 pa4_fifoard0 pa6_pktend pa7_flagd_scls_n gnd vcc sda pb4_fd4 pb3_fd3 pb0_fd0 scl pb1_fd1 pb2_fd2 dplus xtalout xtalin rdy1_slwr avcc avcc agnd rdy0_slrd cy7c68013a-56 l txc u4 le 9 dminus 10 agnd 1 1 vcc 12 gnd 13 ifclk 14 reserved 23 pb5_fd5 24 pb6_fd6 27 vcc 25 pb7_fd7 26 gnd 28 gnd 29 30 31 32 33 34 ctl1_flagb pa1_int1_n ctl0_flaga ctl2_flagc vcc pa0_int0_n 48 47 46 45 44 43 wakeup vcc pd0_fd8 pd1_fd9 pd3_fd11 pd2_fd10 clk d at a 3v3_usb 3v3_usb 3v3_usb c48 10pf c49 0.1f 3v3_usb 3v3_usb r61 2k? cr2 3v3_usb r64 100k? c37 0.1f c45 0.1f r62 100k? 3v3_usb y1 24 mhz 3 4 2 1 c54 22pf c51 22pf 1 2 3 4 5 g1 g2 g3 g4 5v_usb p1 1 2 3 4 5 6 7 8 a0 a1 a2 gnd sda scl wc_n vcc 3v3_usb 3v3_usb 24lc64-i_sn u2 adp3334 u3 1 8 2 3 4 7 6 5 out1 out2 fb nc in2 in1 sd gnd c47 1.0f r65 2k? cr1 5v_usb r69 78.7k? c50 1000pf r70 140k? c52 1.0f 3v3_usb dgnd c35 0.1f c42 0.1f c36 0.1f c41 0.1f c40 0.1f c44 0.1f c46 0.1f 3v3_usb r60 2k? r59 2k? c38 10pf c39 0.1f sdo 09550-084
data sheet adl5336 rev. b | page 27 of 32 figure 72 . silks creen top figure 73 . silks creen bottom 09550-083 09550-082
adl5336 data sheet rev. b | page 28 of 32 bill of materials (b om) table 11. evaluation board configuration options components function default conditions c1, c2, c5, c6, c7, c16, c17, c18, c25, l1, l2 power supply and ground decoupling. nominal supply decoupling consists of 0.1 f capacitor to ground. c 1 , c 2 = 10 f ( 0805 ), c5, c6, c7, c16, c17 = 0.1 f (0402), c18, c25 = 0.1 f (0402), l1, l2 = 33 h (0805) c3, c4, c21, t1 vga1 i nput interface. the balun t1 has a 4:1 impedance ratio that transforms a single - ended signal in a 50 system into a differential signal in a 200 system. c3 and c4 provide ac coupling into vga1, and c21 provides an ac ground for the balun. c3, c4, c21 = 0.1 f (0402), t1 = mini - circuits tc4 -1w c10, c11, c14, c15, c23, c24 , r3, r4, r13 , t4, t5 vga2 i nput interface. the t4 and t5 baluns have 4:1 impedance ratios that transform single - ended signals in a 50 system into differential signals in a 200 system. t he user has a choice of either i nput a or i nput b , which is set by b it b6 in the internal register ( s ee the register map in table 5 ). c11, c14, c15, and c23 provide ac coupling into vga2, and c10 and c24 provide an ac ground for the baluns. r3, r4 , and r13 are left open by default. ac ground can be achieve by placing 0 jumpers at r3 and r4. a 0 jumper can be installed at r13 to drive i nput b of vga2 single ended. note that r4 must be open and r3 must have a 0 jumper installed. c10, c11, c14 = 0.1 f (0402), c15, c23, c24 = 0.1 f (0402), r3, r4, r13 = open (0402) , t 4, t5 = mini - circuits tc4 -1w c8, c9, c22, r14, r15, t2 vga1 o utput interface. the t2 balun has a 4:1 impedance ratio that transforms a differential signal in a 200 system into a single - ended signal in a 50 system. c8 and c9 provide ac coupling out of vga1, and c22 provides an ac ground for the balun. r14 and r15 can be made 0 and dc - couple the output of vga1 into th e input of vga2 in cascadin g applications. c8, c9, c22 = 0.1 f (0402), r14, r15 = open (0402), t2 = mini - circuits tc4 -1w c19, c20, r5, r6, r7, r8, t3 vga2 o utput interface. the transmission line transformer , t3 , has a 1:1 impedance ratio that transforms a differential signal to a single - ended signal. the 50 impedance is the same on both the primary and secondary si de balun. c19 and c20 provide ac coupling out of vga2. r5, r6, r7, and r8 raise the impedance that the output of vga2 sees to 100 differential . c19, c20 = 0.1 f (0402), r5, r6 = 37.4 (0402), r7, r8 = 24.9 (0402), t3 = m/a - com etc1 -1 -13 r1, c12 detector 1 interface. r1 serves as a 0 jumper to connect the integrating cap acitor, c12 , that is needed when vga1 is being used in agc mode. r1 = 0 (0402), c12 = 0.1 f (0402) r2, c13 detector 2 interface. r2 serves as a 0 jumper to connect the inte grating cap acitor, c13 , that is needed when vga2 is being used in agc mode. r2 = 0 (0402), c13 = 0.1 f (0402) p3 enable interface. the adl5336 is powered up by applying a logic high voltage to the enbl pin . jumper p3 is connected to vpos. p3 = installed for enable p2 mode interface. the mode pin must be pulled to a logic high to be used in vga mode. if agc mode is desired, a logic low must be applied to the mode pin. the p2 jumper must be connect ed to eithe r vpos (logic high) or ground (logic low). p2 = installed r9, r10, r11, r12, c26, c27, c28, c29 , p1 serial c ontrol interface. the digital interface sets the vga1 setpoint, vga2 setpoint, vga2 input selection, vga1 max imum gain , and the vga2 max imum gain of the device using the serial interface lines clk, le, data, and sdo. rc filter networks are provided on clk and le lines to filter the pc signals (possibly on all the lines). clk, data, sdo , and le signals can be observed via smb connectors for debug pur poses. r9, r10, r11, r12 = 0 (0402), c26, c27, c28, c29 = open (0402) p5 analog vga1 gain control. the range of the gain1 pin is from 0 v to 1 v, creating a gain scaling of 35 mv/db. p5 installed p4 analog vga2 gain control. the range of the gain2 pin is from 0 v to 1 v, creating a gain scaling of 35 mv/db. p4 installed
data sheet adl5336 rev. b | page 29 of 32 components function default conditions u2, u3, u4 , p1 cypress m icrocontroller, eeprom and ldo u2 = microchip micro24lc64 u3 = a nalo g d evices, inc., adp3334acpz u4 = cypress semiconductor cy7c68013a - 56 lt xc p1 = mini usb connector c35, c36, c40, c41, c42, c44, c46 3.3 v supply decoupling; s everal capacitors are used for decoupling on the 3.3 v supply c35, c36, c40, c41, c42, c44, c46 = 0.1 f (0402) c37, c45, c38, c3 9, c 48, c49, r5 9, r60, r61, r62, r64, cr2 cypress and eeprom components c38, c48 = 10 pf (0402) c37, c39, c45, c49 = 0.1 f (0402) r59, r60, r61 = 2 k (0402) r62, r64 = 100 k (0402) cr2 = rohm sml - 21omtt86 c47, c50, c52, r65, r69, r70, cr1 ldo c omponents c47, c52 = 1 f (0402) c50 = 1000 pf (0402) r65 = 2 k (0402) r69 = 78.7 k (0402) r70 = 140 k (0402) cr1 = rohm sml - 21omtt86 y1, c51, c54 crystal o scillator and compon ents. 24 mhz crystal oscillator y1 = ndk nx3225sa - 24mhz c51, c54 = 22 pf (0402) evaluation board con trol software the adl5336 evaluation board is controlled through the parallel port on a pc. the parallel port is programmed via the adl5336 evaluation software. this software controls the following: ? t he setpoints of vga1 and vga2 ? t he maximum gains of vga1 and vga2 ? t he input control switch of vga2 for information about the register map, see table 5 , table 6 , table 7 , and table 8 . for information about spi port timing and control, see figure 2 and figure 3 . after the software is downloaded and installed, start the basic user interface to program the max imum gains, setpoints , and the input of vga2 , see figure 74. to program the setpoints of each vga, click on the re spective pull - down menu of the desired vga under rms out (mvrms/dbv) , select the desir ed setpoint, and click write bits . to program the maximum gain of each vga , click on the respective pull - down menu of the desired vga under the vga 1 max gain (db)/ vga 2 max gain (db) , select the desired maximum gain, and click write bits . when the user clicks write bits , a write operation execute s , immediately followed by a read operation. the updated information is displayed in the vga1 current state and vga2 current state fields. t he gain displayed does not represent the analog vga gain, only the digital maximum gain. on vga2, the user can switch to either input a or i nput b by selecting the slider switch , vga 2 switch . because the speed of the parallel port varies from pc to pc, the clock stretch function can be used to change the effective frequency of the clk line. the clk line has a scalar range from 1 to 10; 10 is the fastest speed, and 1 is the slowest. figure 74 . adl533 6 software screen capture 09550-084
adl5336 data sheet rev. b | page 30 of 32 outline dimensions figure 75. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adl5336acpz-r7 ?40c to +85c 32-lead lfcsp_vq, 7 tape and reel cp-32-2 ADL5336-EVALZ evaluation board 1 z = rohs compliant part. 3.25 3.10 sq 2.95 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards mo-220-vhhd-2 1 32 8 9 25 24 17 16 coplanarity 0.08 3.50 ref 0.50 bsc pin 1 indicator pin 1 indicator 0.30 0.25 0.18 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom s eating plane 0.50 0.40 0.30 5.00 bsc sq 4.75 bsc sq 0.60 max 0.60 max 0.25 min 05-25-2011-a top view exposed pad bottom view
data sheet adl5336 rev. b | page 31 of 32 notes
adl5336 data sheet rev. b | page 32 of 32 notes ? 2011 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09550 - 0- 2/12(b)

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